Programming With Intel Wireless Mmx Technology,9780974364919

Programming With Intel Wireless Mmx Technology

by ; ;
Edition: CD
ISBN13: 9780974364919
ISBN10: 0974364916
Format: Paperback
Pub. Date: 2004-05-01
Publisher(s): Intel Pr
List Price: $85.52

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Table of Contents

Acknowledgments xi
Part I What is Intel® Wireless MMX™ Technology?
1(86)
Introduction
3(10)
The Growing Need for Mobile Multimedia
4(4)
Technology Drivers
5(2)
Building the Application Base
7(1)
Introducing Intel® Wireless MMX™ Technology
8(1)
Terminology
9(1)
Objectives of the Book
9(4)
Part 1: Introduction to Intel® Wireless MMX™ Technology
9(1)
Part 2: Optimization Techniques
10(1)
Part 3: Case Studies
11(1)
CD-ROM
12(1)
Understanding SIMD Processing
13(12)
What is SIMD?
13(4)
Packing Data
14(1)
Data Types
15(1)
Operating on Packed Data
16(1)
Advantages of SIMD
17(1)
When Should SIMD Processing Be Used?
17(7)
Data Parallelism
17(3)
Data Formatting
20(4)
Inner Loops
24(1)
Key Points
24(1)
Intel® Wireless MMX™ Technology: The Big Picture
25(42)
Packed Data Storage
26(1)
Understanding Instruction Syntax
27(3)
Instruction Format
28(1)
Instruction Prefix
28(1)
Qualifiers
28(2)
Getting the Data
30(6)
Retrieving and Saving Data
30(2)
Aligning Data Elements
32(1)
Transferring a Whole Register to the Core
33(1)
Transferring Elements to the Core
34(2)
Preparing the Data for Processing
36(5)
Extending the precision
36(1)
Reducing Precision
37(1)
Rearranging Data
38(3)
The Basic Operations
41(5)
Addition and Subtraction
43(1)
Logical Operations
44(1)
Shift
45(1)
Comparing Data Elements
46(1)
Signal Processing
47(9)
Multiply Accumulate Instructions
49(4)
Multiply Instructions
53(3)
Video Instructions
56(2)
Sum of Absolute Difference
56(1)
Pixel Average
57(1)
Miscellaneous Instructions
58(3)
Controlling Program Flow
61(4)
SIMD Arithmetic Flags
61(1)
Group Conditional Execution
62(2)
Remembering Saturation
64(1)
Key Points
65(2)
Understanding the Hardware
67(20)
Coprocessor Framework
68(3)
Dealing with Memory
69(1)
The Intel XScale® Microarchitecture
70(1)
Hardware Building Blocks
71(4)
Pipeline Structure Overview
75(6)
Pipelining
75(2)
Terminology
77(1)
Pipeline Structure
78(1)
Pipeline Organization
79(2)
Putting It All Together
81(5)
Understanding How Instructions Execute
81(5)
Issue and Result Latency
86(1)
Key Points
86(1)
Part II Enabling Applications with Intel® Wireless MMX™ Technology
87(168)
The Art of Optimization
89(12)
Optimization Strategy
89(1)
Identifying the Hotspots
90(1)
Pipelined Microprocessors
91(1)
Understanding the Impact of Stalls
91(5)
The Supply of Instructions
91(4)
Finding the Data
95(1)
Identifying Algorithm Techniques
96(2)
Software Pipelining
97(1)
Multi-Sample Calculations
97(1)
Register File Loading
98(1)
Algorithm Fusion
98(1)
Using the Right Approach
98(2)
Getting Started
100(1)
Key Points
100(1)
Finding the Bottleneck
101(20)
Intel® VTune™ Performance Analyzer
103(2)
What Are We Looking For?
103(2)
Before You Begin Sampling
105(2)
Sampling
105(1)
Sample Interval
106(1)
The Plan of Attack
107(2)
Determining the Time Profile
109(3)
Using Events to Analyze Hotspots
112(7)
What Are the Important Events?
112(5)
Deriving Performance Metrics
117(2)
Static Analysis
119(1)
More About VTune Performance Analyzer
120(1)
Key Points
120(1)
Intel® Integrated Performance Primitives
121(22)
What Are the Intel Integrated Performance Primitives (Intel IPP)?
121(3)
Digital Signal Processing Functions
122(1)
Speech Codecs
123(1)
Audio Codecs
123(1)
Image Processing
123(1)
Image and Video Compression
124(1)
Graphics
124(1)
Horizontal and Vertical Functions
124(2)
Where Does Intel IPP Fit with the OS?
126(1)
Why Use Intel IPP?
127(3)
Development Time
127(1)
Code Quality
128(1)
Code Portability
128(2)
When Not to Use Intel IPP
130(1)
Understanding Intel IPP Names
130(1)
The Three Prefixes
131(1)
Fundamental Data Types
132(2)
Signals and Arrays
134(4)
Base Name
134(2)
Modifiers
136(1)
Types
136(1)
Intel GPP Naming Conventions
137(1)
Intel IPP in Action
138(3)
FIR Example
138(1)
MPEG Video Encode
139(2)
What Do You Need to Get Started with Intel IPP?
141(1)
Key Points
141(2)
Embedded Software Development Tool Chain
143(36)
Embedded System Software Design Flow
143(2)
Integrated Design Environment
145(2)
IDE-Based Design Flow
147(2)
Intel C++ Compiler
149(3)
Macroassembler
152(1)
Intel Linker
153(1)
Intel Library Manager
154(1)
Intel Debugger
155(2)
Intrinsic Functions
157(2)
Vectorization Programming Guidelines
159(16)
Making Kernels of the Loop Vectorizer-Friendly
160(4)
Vectorizer-Friendly Addressing
164(2)
Vectorizer-Friendly Loop Organization
166(2)
Data Type Considerations
168(4)
Compiler Directives to Help Vectorization
172(3)
Vectorizer Messages
175(3)
Key Points
178(1)
Optimizing for Memory Subsystems
179(28)
Characteristics of Memory Subsystems
180(1)
Memory Subsystems in Intel Application Processors
180(1)
Memory Subsystems-based Optimization
181(1)
Configuring Memory with the Correct Properties
182(4)
Optimizing Instruction Accesses
184(1)
Optimizing Data Accesses
184(2)
Ensuring Correct Data Objects Placement
186(3)
Reducing the Impact of Data Cache Misses
189(7)
Loading Data Early
189(1)
Preloading Data into the Cache
190(6)
Increasing Memory Throughput
196(4)
Utilizing the Nonblocking Multiple Loads
197(2)
Utilizing Write Combining
199(1)
Programming Techniques for Memory and Cache Efficiency
200(6)
Choosing Data Types and Alignment
201(1)
Increasing Cache Locality
201(3)
Intelligent Addressing for Reducing Cache Eviction
204(1)
Increasing Data Reuse
205(1)
Key Points
206(1)
Optimizing for Pipelines
207(26)
Microarchitectural Optimization Philosophy
208(1)
Choosing the Right Instruction
208(1)
Choosing the Right Sequence
209(1)
Stall-Directed Instruction Scheduling
209(4)
Looking for Stalls
210(1)
Avoiding Stalls
210(2)
Decomposition of an Application
212(1)
Optimization for Data-Processing Operations
213(10)
Fast Multiply Operations
213(2)
Fast Multiply and Accumulation
215(2)
Scheduling in the Addition and Logical Pipeline
217(1)
Getting Data from Cache to Register and Back Efficiently
218(4)
Optimizing Align and Shift
222(1)
Optimization for Control-Oriented Operations
223(9)
Reduce Branch Cost
223(1)
Use Conditional Instruction
224(5)
Use Addressing Modes Efficiently
229(1)
Miscellaneous Approaches
230(2)
Key Points
232(1)
Porting Existing Code
233(22)
Application Porting
233(2)
Porting Options
234(1)
Intel® MMX™ and SSE Technology Mapping
235(2)
Instruction Syntax
235(2)
Understanding the Differences
237(10)
Terminology
237(2)
Data Storage
239(1)
Instruction Operands
239(2)
Memory Operands
241(1)
New Instruction Capability
242(5)
Case Studies of Code Porting
247(4)
Complex Multiply by a Constant
247(1)
Absolute Difference of Unsigned Numbers
248(1)
Absolute Difference of Signed Numbers
248(1)
Reducing Precision with an Interleaved Pack
249(1)
Alpha Saturation
250(1)
Porting Code Using C-Intrinsics
251(3)
Key Points
254(1)
Part III Intel® Wireless MMX™ Technology Case Studies
255(170)
Accelerating Graphics Applications
257(40)
Graphics Pipeline
257(2)
Indicators of Performance
259(1)
Fill Rate
259(1)
Polygon Rate
260(1)
Optimization Challenges
260(3)
Performance Profile
260(3)
Performance Optimization Methods
263(10)
Algorithmic Optimization
264(1)
Computational Optimization
264(4)
Memory-Related Optimization
268(5)
Optimizing Graphics Application Kernels
273(22)
Shading
273(22)
Key Points
295(2)
Digital Signal Processing
297(36)
DSP Fundamentals
297(5)
Digital Signals
298(3)
Digital Filters
301(1)
FIR Filters
302(16)
Memory Organization for the FIR Filter
304(2)
Computing the FIR Filter
306(12)
IIR Filters
318(5)
Computing the Biquad IIR Filter
320(3)
Adaptive Filtering
323(8)
FIR-LMS Algorithm
324(2)
Computing the Single Sample FIR-LMS Filter
326(5)
Key Points
331(2)
Digital Image Processing
333(38)
Image Processing Fundamentals
334(8)
Digital Images
335(2)
Color Space
337(3)
Digital Cameras
340(2)
Image Filtering
342(13)
Spatial Convolution
343(4)
Filtering with Non-separable Kernels
347(5)
Filtering with Separable Kernels
352(3)
Color Synthesis
355(8)
Nearest Neighbor Replication
357(2)
Color Synthesis Using NNR
359(4)
Color Correction
363(5)
Color Correcting the RGB Image
364(4)
Key Points
368(3)
H.264 and MPEG-4 Video Compression
371(54)
Video Fundamentals
371(2)
Macroblocks
372(1)
MPEG Video Compression
373(14)
Video Codec
374(4)
Motion Estimation and Compensation
378(6)
2D Discrete Cosine Transforms (DCT)
384(2)
Quantization
386(1)
Entropy Encoding
386(1)
Intel® Wireless MMX™ in Motion Estimation and Compensation
387(36)
Computing the Block SAD
387(6)
Fixed Pattern Motion Estimation
393(15)
Motion Compensation with Intel Wireless MMX Technology
408(1)
P-Type Pictures
408(7)
B-Type Pictures
415(8)
Key Points
423(2)
References 425(2)
Index 427

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